Practical ESD Protection Design
- Length: 432 pages
- Edition: 1
- Language: English
- Publisher: Wiley-IEEE Press
- Publication Date: 2021-12-29
- ISBN-10: 1119850401
- ISBN-13: 9781119850403
- Sales Rank: #9103187 (See Top 100 Books)
An authoritative single-volume reference on the design and testing of electrostatic discharge (ESD) structures
Electrostatic discharge (ESD) is a serious challenge to the reliability of semiconductors, integrated circuits (ICs), and microelectronic systems—on-chip ESD protection is a vital component of smartphones, laptops, tablets, and other electronic devices. Practical ESD Protection Design provides comprehensive and systematic guidance on all major aspects of on-chip ESD protection for integrated circuits (ICs).
Written for students and practicing engineers alike, this one-stop resource covers essential theories, hands-on design skills, computer-aided design (CAD) methods, ESD failure testing and analysis, and more. Detailed chapters examine an array of topics ranging from fundamental to advanced, including ESD phenomena, ESD protection devices and circuits, ESD design layout and technology effects, emerging ESD protection designs, and circuit simulation modelling. Based on the author’s decades of design, teaching, and research experience, Practical ESD Protection Design:
- Features numerous real-world examples of electrostatic discharge (ESD) protection designs and skills
- Describes the design methodology for high-performance mixed-signal ICs and broadband radio-frequency (RF) ICs
- Discusses CAD-based ESD protection design using existing tools such as Technology Computer-Aided Design (TCAD) and SPICE simulation
- Addresses new ESD CAD algorithms and tools for full-chip ESD physical design verification
- Explores the disruptive future outlook of ESD protection
Practical ESD Protection Design is a valuable reference for industrial engineers and academic researchers in the field, and an excellent textbook for electronic engineering courses in semiconductor microelectronics and integrated circuit design.
Cover Table of Contents Title Page Copyright Author Biography Preface 1 Why ESD? 1.1 A Historical Perspective 1.2 ESD and the Dangers 1.3 ESD Protection: The Principles 1.4 ESD Protection: More or Less? 1.5 ESD Protection: Evolution to Revolution References 2 ESD Failure Analysis 2.1 ESD Failure Analysis 2.2 ESD FA Techniques 2.3 ESD Failure Signatures 2.4 ESD Soft Failures 2.5 ESD Failure Correlation 2.6 ESD Failure Models References 3 ESD Test Models and Standards 3.1 ESD Origins 3.2 HBM Model 3.3 MM Model 3.4 CDM Model 3.5 IEC Model 3.6 TLP Model 3.7 Summary References 4 ESD Protection Devices 4.1 On-Chip ESD Protection Mechanisms 4.2 Diode for ESD Protection 4.3 BJT for ESD Protection 4.4 MOSFET for ESD Protection 4.5 SCR for ESD Protection 4.6 Summary References 5 ESD Protection Circuits 5.1 I/O ESD Protection 5.2 ESD Self-Protection 5.3 Low-Triggering ESD Protection Circuits 5.4 ESD Power Clamps 5.5 Summary References 6 Full-Chip ESD Protection 6.1 Full-Chip ESD Protection Principles 6.2 ESD Protection Design Window 6.3 Advanced ESD Protection: More at Less 6.4 Full-Chip ESD Protection Schemes 6.5 No Universal ESD Protection Solution References 7 Mixed-Signal and HV ESD Protection 7.1 ESD Protection for Mixed-Signal ICs 7.2 ESD Protection for Multiple-Voltages ICs 7.3 ESD Protection for High-Voltage ICs 7.4 Summary References 8 TCAD-Based Mixed-Mode ESD Protection Designs 8.1 ESD Design Optimization and Prediction 8.2 TCAD-Based Mixed-Mode ESD Simulation-Design Methodology 8.3 Mixed-Mode ESD Simulation-Design Examples 8.4 Summary References 9 RF ESD Protection 9.1 What Is Special for RF ESD Protection? 9.2 RF ESD Protection Characterization 9.3 Low-Parasitic ESD Protection Solutions 9.4 RF ESD Protection Design Example 9.5 Summary References 10 ESD-RFIC Co-Design 10.1 ESD-IC Interactions 10.2 ESD-RFIC Co-Design 10.3 Summary References 11 ESD Layout Designs 11.1 Layout is Critical to ESD Protection 11.2 Basic ESD Protection Layout 11.3 Advanced ESD Protection Layout 11.4 3D TCAD for ESD Layout Designs 11.5 Summary References 12 ESD versus IC Technologies 12.1 IC Technologies and ESD Protection 12.2 Technology Affects ESD Design Window 12.3 Lowering ESD Protection for Advanced ICs? 12.4 Summary References 13 ESD Circuit Simulation by SPICE 13.1 ESD Device Behavior Modeling 13.2 Full‐Chip ESD Circuit Simulation by SPICE 13.3 Summary References 14 Emerging ESD Protection 14.1 Emerging ESD Protection Challenges 14.2 Dispensable ESD Protection 14.3 Field‐Programmable ESD Protection 14.4 Interposer/TSV‐Based ESD Protection 14.5 Summary References 15 ESD CAD for Full‐Chip Design Verification 15.1 Full‐Chip ESD Design Verification 15.2 CAD Algorithms for ESD Design Verification 15.3 Full‐Chip ESD Design Verification Examples 15.4 Summary References 16 New CDM ESD Protection 16.1 Misconception in CDM ESD Protection 16.2 Analyzing Pad‐Based CDM ESD Protection 16.3 Internally Distributed CDM ESD Protection 16.4 Summary References 17 Future ESD Protection Outlook 17.1 The Fundamental ESD Protection Problem 17.2 Above‐IC Nano‐Crossbar Array ESD Switch 17.3 Graphene ESD Protection Switch 17.4 Graphene ESD Protection Interconnects 17.5 Future ESD Protection Outlook 17.6 Summary References Index End User License Agreement
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