IP Core Protection and Hardware-Assisted Security for Consumer Electronics
- Length: 552 pages
- Edition: 1
- Language: English
- Publisher: The Institution of Engineering and Technology
- Publication Date: 2019-03-25
- ISBN-10: 1785617990
- ISBN-13: 9781785617997
- Sales Rank: #7761281 (See Top 100 Books)
IP Core Protection and Hardware-Assisted Security for Consumer Electronics presents established and novel solutions for security and protection problems related to IP cores (especially those based on DSP/multimedia applications) in consumer electronics. The topic is important to researchers in various areas of specialization, encompassing overlapping topics such as EDA-CAD, hardware design security, VLSI design, IP core protection, optimization using evolutionary computing, system-on-chip design and application specific processor/hardware accelerator design.
The book begins by introducing the concepts of security, privacy and IP protection in information systems. Later chapters focus specifically on hardware-assisted IP security in consumer electronics, with coverage including essential topics such as hardware Trojan security, robust watermarking, fingerprinting, structural and functional obfuscation, encryption, IoT security, forensic engineering based protection, JPEG obfuscation design, hardware assisted media protection, PUF and side-channel attack resistance.
Cover Title Copyright Contents About the authors Acknowledgments Foreword by Thomas M. Coughlin Foreword by Pradipta Patra Foreword by Swarup Bhunia Foreword by Peter Corcoran Preface List of acronyms List of notations 1 Introduction to IP core protection and hardware-assisted security of consumer electronics 1.1 Consumer electronics and security perspectives 1.2 Hardware-assisted security and IP core protection 1.3 Intellectual property (IP) cores/hardware 1.3.1 Utility of IP cores in CE devices 1.3.2 Why security and protection of hardware/IP cores? 1.3.3 Traditional forms of IP protection not enough? 1.4 IP core protection and hardware-assisted security of CE device—DSP core 1.4.1 Security and protection methodologies available for IP core/hardware 1.4.2 Different IP core protection and hardware-assisted security mechanisms: advantages and disadvantages 1.4.3 HLS (architectural synthesis) as design backbone for implementing security algorithms for DSP IP cores 1.5 Hardware-assisted media protection 1.6 Physical unclonable functions 1.7 Organization of the book 1.8 Conclusions 1.9 Exercises References 2 Security in consumer electronics and internet of things (IoT) 2.1 Internet of things (IoT) – a broad overview 2.1.1 IoT – architecture 2.1.2 IoT – driving technology 2.1.3 IoT – applications 2.1.4 IoT – challenges 2.2 Security, privacy, IPR in IoT, and consumer electronic systems – a big picture 2.2.1 IoT security – attacks and countermeasures 2.2.2 Trustworthy consumer electronic systems 2.2.3 Hardware-assisted security and protection 2.2.4 Different aspects of security and privacy 2.2.5 Different aspects of intellectual property (IP), ownership right, or copyright protection 2.3 Memory security 2.3.1 Memory security attacks 2.3.2 Memory security solutions 2.4 Radio-frequency identification (RFID) security 2.4.1 RFID security attacks 2.4.2 RFID security solutions 2.5 Near-field communications (NFC) security 2.5.1 NFC security attacks 2.5.2 NFC security solutions 2.6 Smart transportation security 2.6.1 Smart car security 2.6.2 UAV or drone security 2.7 Smart healthcare security 2.7.1 Smart healthcare security attacks 2.7.2 Smart healthcare security solutions 2.8 Firmware 2.8.1 Firmware attacks 2.8.2 Firmware solutions 2.9 Blockchain technology 2.9.1 Blockchain – overview 2.9.2 Blockchain – application 2.9.3 Blockchain as a security framework 2.9.4 Blockchain – issues 2.10 Conclusions 2.11 Exercises References 3 Trojan security aware DSP IP core and integrated circuits 3.1 Introduction 3.2 Types of hardware Trojans 3.2.1 Trojan features 3.2.2 Benefit of Trojan security at higher abstraction level 3.2.3 Threat model 3.3 Hardware Trojan in a 3PIP module 3.3.1 Example of a hardware Trojan 3.3.2 Trojan detectability in a 3PIP module at RTL/lower levels 3.4 Selected Trojan security approaches 3.4.1 Trojan security approaches for DSP cores 3.4.2 Trojan security approach for combinational/sequential circuits 3.5 Trojan security aware DSP IP core 3.5.1 Definition 3.5.2 Goal 3.5.3 Formulation 3.5.4 Models 3.6 Design process of Trojan secured DSP IP core 3.6.1 Deriving the CDFG of a DSP core 3.6.2 Generating the DMR of the CDFG 3.6.3 Trojan secured scheduling of DMR CDFG 3.7 Analysis of case studies/test cases 3.7.1 DSP applications and system setup for the case studies 3.7.2 Security analysis 3.7.3 Design cost analysis 3.7.4 Comparative perspectives 3.8 Conclusion 3.9 Exercises References 4 IP core and integrated circuit protection using robust watermarking 4.1 Introduction 4.2 Selected watermarking approaches 4.3 Design process of watermarked IP core/hardware 4.3.1 Problem formulation 4.3.2 Design process of single-phase watermarked IP core/hardware 4.3.3 Design process of triple-phase watermarked IP core/hardware 4.3.4 Desired properties of IP core watermark 4.3.5 Possible cases of dishonest claim of IP core/hardware ownership and its resolution 4.4 Analysis on case studies 4.4.1 Security analysis of triple-phase watermark for DSP IP cores 4.4.2 Design cost analysis of triple-phase watermark for DSP IP cores 4.5 Conclusion 4.6 Exercises References 5 Symmetrical protection of DSP IP core and integrated circuits using fingerprinting and watermarking 5.1 Introduction 5.1.1 Background on watermark and fingerprint 5.1.2 Threat model 5.1.3 Benefits of protection at higher abstraction 5.2 Fundamentals of IP core protection 5.2.1 Overview on non-symmetric IP core protection techniques 5.2.2 Overview on symmetric IP core protection techniques 5.3 Symmetrical IP core protection for DSP core 5.3.1 Problem formulation 5.3.2 Symmetrically protected design—area evaluation model 5.3.3 Symmetrically protected design—delay evaluation model 5.3.4 Symmetrically protected design—cost evaluation function 5.3.5 Encoding rules of buyer fingerprint and seller watermark for DSP IP cores 5.3.6 Multi-variable signature embedding process 5.3.7 Signature detection process 5.3.8 Desirable properties of signature 5.4 Case study of symmetrical IP core protection 5.4.1 Demonstration of fingerprinting constraints embedding process 5.4.2 Demonstration of watermarking constraints embedding process 5.5 Analysis of case studies for DSP cores 5.5.1 Analysis of embedding cost, security metric on DSP Cores symmetrical protection 5.5.2 Comparative study between symmetrical and non-symmetrical technique 5.6 Conclusion 5.7 Exercises References 6 Computational forensic engineering for resolving ownership conflict of DSP IP core 6.1 Introduction 6.1.1 Overview of forensic engineering 6.2 Computational FE technology 6.3 IP core feature extraction algorithms 6.3.1 Feature extraction rules 6.3.2 IP core validation 6.3.3 Important characteristics of customized CFE 6.4 Analysis on case studies 6.4.1 Results of the customized CFE approach 6.5 Conclusion 6.6 Exercises References 7 Structural obfuscation of DSP cores used in CE devices 7.1 Introduction 7.1.1 Threat model 7.1.2 Benefits of providing security at higher design abstraction level 7.2 Obfuscation for IP core protection—a broad view 7.2.1 Code obfuscation techniques 7.2.2 Logic obfuscation techniques 7.2.3 Structural obfuscation techniques 7.3 Compiler transformation-driven structural obfuscation 7.3.1 Formulation and evaluation models 7.3.2 Multistage high-level transformation techniques 7.4 Low-cost structural obfuscation for DSP IP core 7.4.1 Overview on PSO 7.4.2 Movement of particle 7.4.3 Terminating condition of PSO 7.5 A case study for multistage structural obfuscation 7.6 Analysis of case studies 7.6.1 Result of multistage structural obfuscation 7.6.2 Comparative study and discussion 7.7 Conclusion 7.8 Exercises References 8 Functional obfuscation of DSP cores used in CE devices 8.1 Introduction 8.2 Attack scenarios and threat model 8.2.1 Possible attack scenarios 8.2.2 Threat model 8.3 Selected functional obfuscation approaches 8.4 Design of functionally obfuscated DSP core 8.4.1 Formulation 8.4.2 Low-cost obfuscation method for DSP core 8.5 Security of functionally obfuscated DSP core design 8.5.1 Keyspace 8.5.2 Security analysis 8.5.3 Countermeasures against attacks 8.6 Optimization engine for functional obfuscation of DSP cores 8.6.1 Particle encoding 8.6.2 Particle fitness 8.6.3 Updating particle 8.7 Analysis of case studies 8.7.1 Security analysis 8.7.2 Overhead analysis 8.7.3 Comparative analysis 8.8 Conclusion 8.9 Exercises References 9 Obfuscation of JPEG CODEC IP core for CE devices 9.1 Introduction 9.2 Overview of JPEG compression and decompression 9.2.1 DCT-based JPEG image compression process 9.2.2 DCT-based JPEG image decompression process 9.3 Design process of structurally obfuscated JPEG IP core 9.3.1 Threat model, problem formulation, and optimization framework 9.3.2 Constructing non-obfuscated DFG for JPEG compression 9.3.3 Generating structurally obfuscated JPEG compression IP core 9.3.4 Generating structurally obfuscated JPEG decompression IP core 9.4 Implementation of JPEG CODEC IP core 9.4.1 Designing obfuscated JPEG compression IP core 9.4.2 Designing obfuscated JPEG decompression IP core 9.4.3 End-to-end JPEG CODEC through designed hardware/IP core 9.5 Analysis on case studies 9.6 Conclusion 9.7 Exercises References 10 Advanced encryption standard (AES) and its hardware watermarking for ownership protection 10.1 Introduction 10.2 AES algorithm 10.2.1 Overview of AES 10.2.2 AES algorithm—description and custom hardware design 10.3 AES digital watermarking 10.3.1 AES watermark encoding 10.3.2 Process of embedding watermark in AES 10.3.3 Signature detection 10.4 Case study of a watermarked AES hardware 10.5 Conclusion 10.6 Exercises References 11 Hardware approaches for media and information protection and authentication 11.1 IP Protection—a broad overview 11.1.1 Digital rights management 11.1.2 Copyright protection of multimedia—a brief history 11.1.3 Hardware versus media protection 11.2 General framework for copyright protection 11.2.1 The encoder 11.2.2 The decoder 11.2.3 The comparator 11.3 Types of digital watermarks 11.3.1 Spatial versus frequency domain watermarking 11.3.2 Based on multimedia objects 11.3.3 Based on human perception 11.3.4 From applications point of view 11.3.5 Based on embedding techniques 11.3.6 Hardware-based watermarking systems 11.4 Applications of digital watermarks 11.4.1 Copyright protection 11.4.2 Ownership assertion 11.4.3 Authentication and integrity verification 11.4.4 Fingerprinting 11.4.5 Usage control 11.4.6 Broadcast monitoring 11.4.7 Content labeling 11.4.8 Misappropriation detection 11.4.9 Anti-counterfeiting 11.4.10 UAV safety 11.4.11 Medical signals authentication 11.5 Desired characteristics of watermarks 11.5.1 Perceptibility 11.5.2 Robustness 11.5.3 Tamper resistance 11.5.4 Bit rate 11.5.5 Modifiability, multiplicity, cascadability, and orthogonality 11.5.6 Scalability 11.5.7 Unambiguity and universality 11.5.8 Pixel alteration and human intervention 11.5.9 Reliability 11.5.10 Blindness 11.5.11 Security 11.5.12 Real-time operation 11.5.13 Cost and complexity 11.5.14 Energy consumption 11.5.15 Integrability 11.5.16 Characteristics specific to a watermark 11.6 Technical challenges for watermarking 11.6.1 Properties of visual signals 11.6.2 Properties of the human visual system 11.6.3 How much watermark signal to add and where? 11.6.4 Spread spectrum communications 11.7 Hardware-based approaches for watermarking 11.7.1 Image watermarking hardware systems 11.7.2 Video watermarking hardware systems 11.7.3 Secure better portable graphics (SBPG) 11.7.4 Trust cam 11.8 Dynamic watermarking in smart car or UAV 11.9 Medical signals authentication 11.10 Side-channel information leakage attacks and countermeasures 11.10.1 An encryption hardware 11.10.2 Side-channel analysis attacks 11.10.3 Side-channel attack countermeasures 11.11 Attacks on watermarks and watermarking systems 11.11.1 Removal and interference attacks 11.11.2 Geometric attacks 11.11.3 Cryptographic attacks 11.11.4 Protocol attacks 11.12 Limitations of watermarks and watermarking 11.13 Conclusion 11.14 Exercises References 12 Physical unclonable functions (PUFs) 12.1 Introduction 12.2 PUF: Principle 12.3 Properties or characteristics of PUFs 12.3.1 Uniqueness 12.3.2 Reliability (correctness) 12.3.3 Randomness (uniformity) 12.3.4 Correlation (bit aliasing) 12.3.5 Power consumption 12.3.6 Speed 12.4 Classification of PUFs 12.4.1 Device-based PUFs 12.4.2 Security-based PUFs 12.5 Ring oscillator–based PUFs 12.6 Reconfigurable or dynamic PUFs 12.7 SRAM-based PUF 12.8 Memristor-based PUFs 12.9 Diode-based PUF 12.10 Carbon-based PUFs 12.10.1 CNT-based PUF 12.10.2 Graphene-based PUF 12.11 Microprocessor-based PUF 12.12 Magnetic PUF 12.13 Practical implementation of PUF 12.14 PUF: case study applications 12.15 PUF: issues 12.16 Conclusion 12.17 Exercises References Appendix A Appendix B Index
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