Fundamentals of Logic Design, 7th Edition
- Length: 816 pages
- Edition: 7
- Language: English
- Publisher: Cengage Learning
- Publication Date: 2020-01-01
- ISBN-10: 1337620351
- ISBN-13: 9781337620352
- Sales Rank: #1071877 (See Top 100 Books)
Master the principles of logic design with the exceptional balance of theory and application found in Roth/Kinney/John’s FUNDAMENTALS OF LOGIC DESIGN, ENHANCED, 7th Edition. This edition introduces you to today’s latest advances. The authors have carefully developed a clear presentation that introduces the fundamental concepts of logic design without overwhelming you with the mathematics of switching theory. Twenty engaging, easy-to-follow study units present basic concepts, such as Boolean algebra, logic gate design, flip-flops and state machines. You learn to design counters, adders, sequence detectors and simple digital systems. After mastering the basics, you progress to modern design techniques using programmable logic devices as well as VHDL hardware description language.
Cover Dedication Contents Preface How to Use This Book for Self-Study Digital Resources About the Authors Unit 1: Introduction Number Systems and Conversion Objectives Study Guide 1.1 Digital Systems and Switching Circuits 1.2 Number Systems and Conversion 1.3 Binary Arithmetic 1.4 Representation of Negative Numbers 1.5 Binary Codes Problems Unit 2: Boolean Algebra Objectives Study Guide 2.1 Introduction 2.2 Basic Operations 2.3 Boolean Expressions and Truth Tables 2.4 Basic Theorems 2.5 Commutative, Associative, Distributive, and DeMorgan's Laws 2.6 Simplification Theorems 2.7 Multiplying Out and Factoring 2.8 Complementing Boolean Expressions Problems Unit 3: Boolean Algebra (Continued) Objectives Study Guide 3.1 Multiplying Out and Factoring Expressions 3.2 Exclusive-OR and Equivalence Operations 3.3 The Consensus Theorem 3.4 Algebraic Simplification of Switching Expressions 3.5 Proving Validity of an Equation Programmed Exercise 3.1 Programmed Exercise 3.2 Problems Unit 4: Applications of Boolean Algebra Minterm and Maxterm Expansions Objectives Study Guide 4.1 Conversion of English Sentences to Boolean Equations 4.2 Combinational Logic Design Using a Truth Table 4.3 Minterm and Maxterm Expansions 4.4 General Minterm and Maxterm Expansions 4.5 Incompletely Specified Functions 4.6 Examples of Truth Table Construction 4.7 Design of Binary Adders and Subtracters Problems Unit 5: Karnaugh Maps Objectives Study Guide 5.1 Minimum Forms of Switching Functions 5.2 Two- and Three-Variable Karnaugh Maps 5.3 Four-Variable Karnaugh Maps 5.4 Determination of Minimum Expressions Using Essential Prime Implicants 5.5 Five-Variable Karnaugh Maps 5.6 Other Uses of Karnaugh Maps 5.7 Other Forms of Karnaugh Maps Programmed Exercise 5.1 Problems Unit 6: Quine-McCluskey Method Objectives Study Guide 6.1 Determination of Prime Implicants 6.2 The Prime Implicant Chart 6.3 Petrick’s Method 6.4 Simplification of Incompletely Specified Functions 6.5 Simplification Using Map-Entered Variables 6.6 Conclusion Programmed Exercise 6.1 Problems Unit 7: Multi-Level Gate Circuits NAND and NOR Gates Objectives Study Guide 7.1 Multi-Level Gate Circuits 7.2 NAND and NOR Gates 7.3 Design of Two-Level NAND- and NOR-Gate Circuits 7.4 Design of Multi-Level NAND- and NOR-Gate Circuits 7.5 Circuit Conversion Using Alternative Gate Symbols 7.6 Design of Two-Level, Multiple-Output Circuits 7.7 Multiple-Output NAND- and NOR-Gate Circuits Problems Unit 8: Combinational Circuit Design and Simulation Using Gates Objectives Study Guide 8.1 Review of Combinational Circuit Design 8.2 Design of Circuits with Limited Gate Fan-In 8.3 Gate Delays and Timing Diagrams 8.4 Hazards in Combinational Logic 8.5 Simulation and Testing of Logic Circuits Problems Design Problems Unit 9: Multiplexers, Decoders, and Programmable Logic Devices Objectives Study Guide 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field-Programmable Gate Arrays Problems Unit 10: Introduction to VHDL Objectives Study Guide 10.1 VHDL Description of Combinational Circuits 10.2 VHDL Models for Multiplexers 10.3 VHDL Modules 10.4 Signals and Constants 10.5 Arrays 10.6 VHDL Operators 10.7 Packages and Libraries 10.8 IEEE Standard Logic 10.9 Compilation and Simulation of VHDL Code Problems Design Problems Unit 11: Latches and Flip-Flops Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated Latches 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with Additional Inputs 11.9 Asynchronous Sequential Circuits 11.10 Summary Problems Programmed Exercise 11.35 Unit 12: Registers and Counters Objectives Study Guide 12.1 Registers and Register Transfers 12.2 Shift Registers 12.3 Design of Binary Counters 12.4 Counters for Other Sequences 12.5 Counter Design Using S-R and J-K Flip-Flops 12.6 Derivation of Flip-Flop Input Equations-Summary Problems Unit 13: Analysis of Clocked Sequential Circuits Objectives Study Guide 13.1 A Sequential Parity Checker 13.2 Analysis by Signal Tracing and Timing Charts 13.3 State Tables and Graphs 13.4 General Models for Sequential Circuits Programmed Exercise 13.1 Problems Unit 14: Derivation of State Graphs and Tables Objectives Study Guide 14.1 Design of a Sequence Detector 14.2 More Complex Design Problems 14.3 Guidelines for Construction of State Graphs 14.4 Serial Data Code Conversion 14.5 Alphanumeric State Graph Notation 14.6 Incompletely Specified State Tables Programmed Exercise 14.1 Problems Unit 15: Reduction of State Tables State Assignment Objectives Study Guide 15.1 Elimination of Redundant States 15.2 Equivalent States 15.3 Determination of State Equivalence Using an Implication Table 15.4 Equivalent Sequential Circuits 15.5 Reducing Incompletely Specified State Tables 15.6 Derivation of Flip-Flop Input Equations 15.7 Equivalent State Assignments 15.8 Guidelines for State Assignment 15.9 Using a One-Hot State Assignment Problems Unit 16: Sequential Circuit Design Objectives Study Guide 16.1 Summary of Design Procedure for Sequential Circuits 16.2 Design Example-Code Converter 16.3 Design of Iterative Circuits 16.4 Design of Sequential Circuits Using ROMs and PLAs 16.5 Sequential Circuit Design Using CPLDs 16.6 Sequential Circuit Design Using FPGAs 16.7 Simulation and Testing of Sequential Circuits 16.8 Overview of Computer-Aided Design Design Problems Additional Problems Unit 17: VHDL for Sequential Logic Objectives Study Guide 17.1 Modeling Flip-Flops Using VHDL Processes 17.2 Modeling Registers and Counters Using VHDL Processes 17.3 Modeling Combinational Logic Using VHDL Processes 17.4 Modeling a Sequential Machine 17.5 Synthesis of VHDL Code 17.6 More about Processes and Sequential Statements Problems Simulation Problems Unit 18: Circuits for Arithmetic Operations Objectives Study Guide 18.1 Serial Adder with Accumulator 18.2 Design of a Binary Multiplier 18.3 Design of a Binary Divider Programmed Exercise 18.1 Problems Unit 19: State Machine Design with SM Charts Objectives Study Guide 19.1 State Machine Charts 19.2 Derivation of SM Charts 19.3 Realization of SM Charts Problems Unit 20: VHDL for Digital System Design Objectives Study Guide 20.1 VHDL Code for a Serial Adder 20.2 VHDL Code for a Binary Multiplier 20.3 VHDL Code for a Binary Divider 20.4 VHDL Code for a Dice Game Simulator 20.5 Concluding Remarks Problems Lab Design Problems Appendix A: MOS and CMOS Logic Appendix B: VHDL Language Summary Appendix C: Tips for Writing Synthesizable VHDL Code Appendix D: Proofs of Theorems Appendix E: Answers to Selected Study Guide Questions and Problems References Index Description of the CD
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