Application-Specific Hardware Architecture Design with VHDL
- Length: 196 pages
- Edition: 1
- Language: English
- Publisher: Springer
- Publication Date: 2017-10-20
- ISBN-10: 3319650246
- ISBN-13: 9783319650241
- Sales Rank: #0 (See Top 100 Books)
This book guides readers through the design of hardware architectures using VHDL for digital communication and image processing applications that require performance computing. Further it includes the description of all the VHDL-related notions, such as language, levels of abstraction, combinational vs. sequential logic, structural and behavioral description, digital circuit design, and finite state machines. It also includes numerous examples to make the concepts presented in text more easily understandable.
Contents Intro to Digital Design with VHDL Digital Systems—Introductory Notes Levels of Abstraction The VHDL Hardware Description Language Overview of Hardware Description Languages VHDL Code Structure Data Types and Operators Combinational Logic, Sequential Logic and VHDL Concurrent VHDL Code Sequential VHDL Code Structural Description with VHDL VHDL Code for Simulation Test-Benches Finite State Machines Methodology for Digital Design with VHDL Conclusions Appendix A Appendix B Appendix C References Architectures for Channel Encoding in Information Transmission Systems Introduction to Information Transmission System Modelling an Information Transmission System Introduction to Channel Encoding for Error Control Representation of Error Control Codes Classi fi cation of Error Control Codes Error Control Codes Parameters Block Codes Coding Equations Decoding Equations Hamming Coder/Decoder Implementations Encoder Implementation Cyclic Codes Principles Cyclic Codes Encoder and Decoder Implementations Cyclic Decoder Architectures Conclusions References High-Throughput Architecture for LDPC Decoders Introduction to LDPC Codes for Digital Communication Decoding Algorithms Description Low-Complexity Approach for LDPC Decoding Process Conclusions References Architecture for Edge Detection Introduction—Microarray Image Processing System Hardware Architecture for Image Convolution Convolution in Digital Image Processing Hardware Implementation for Convolution Hardware Architecture for the Canny Filter Canny Edge Detection Hardware Implementation of the Canny Edge Detector Timing Considerations for the Canny Edge Detection Architecture System-on-a-Chip (SoC) for Edge Detection Canny Architecture Applied in Microarray Image Processing Appendix D References Architectures for Iterative Algorithms Implementations Hardware Architecture for Shock Filters Applied in Microarray Image Processing Partially Differential Equations in Image Processing Shock Filters Shock Filter Application—Microarray Grid Alignment Hardware Architecture for Shock Filters Timing Considerations Hardware Architecture for Anisotropic Diffusion Applied in Satellite Imagery Introduction to Satellite Imagery Perona and Malik Filter Formulation Hardware Implementation for Parallel Computation of Anisotropic Diffusion Application-Speci fi c Hardware Architecture for Perona and Malik Filter in Satellite Imagery—Case Study Conclusions References Efficient Hough Transform Implementation using CAM Memories applied on Satellite Imagery Satellite Imagery for Oil Slick Detection Circular Hough Transform CAM-Based Approach for Ef fi cient Hough Transform Implementation Memory Implementation Using FPGA Memory Types Inferred and Instantiated Memories Using VHDL Memory Organization CAM Memory Implementation Using VHDL Conclusions References
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