The newest addition to the Harris and Harris family of Digital Design and Computer Architecture books, this RISC-V Edition covers the fundamentals of digital logic design and reinforces logic concepts through the design of a RISC-V microprocessor. Combining an engaging and humorous writing style with an updated and hands-on approach to digital design, this book takes the reader from the fundamentals of digital logic to the actual design of a processor. By the end of this book, readers will be able to build their own RISC-V microprocessor and will have a top-to-bottom understanding of how it works.
Beginning with digital logic gates and progressing to the design of combinational and sequential circuits, this book uses these fundamental building blocks as the basis for designing a RISC-V processor. SystemVerilog and VHDL are integrated throughout the text in examples illustrating the methods and techniques for CAD-based circuit design. The companion website includes a chapter on I/O systems with practical examples that show how to use SparkFun’s RED-V RedBoard to communicate with peripheral devices such as LCDs, Bluetooth radios, and motors.
This book will be a valuable resource for students taking a course that combines digital logic and computer architecture or students taking a two-quarter sequence in digital logic and computer organization/architecture.
Inside Back Cover Front-matter Copyright Page Contents Preface About the Authors 1 From Zero to One 1.1 The Game Plan 1.2 The Art of Managing Complexity Abstraction Discipline The Three -Y’s 1.3 The Digital Abstraction 1.4 Number Systems Decimal Numbers Binary Numbers Hexadecimal Numbers Bytes, Nibbles, and All That Jazz Binary Addition Signed Binary Numbers Sign/Magnitude Numbers Two’s Complement Numbers Comparison of Number Systems 1.5 Logic Gates NOT Gate Buffer AND Gate OR Gate Other Two-Input Gates Multiple-Input Gates 1.6 Beneath the Digital Abstraction Supply Voltage Logic Levels Noise Margins DC Transfer Characteristics The Static Discipline 1.7 Cmos Transistors* Semiconductors Diodes Capacitors nMOS and pMOS Transistors CMOS NOT Gate Other CMOS Logic Gates Transmission Gates Pseudo-nMOS Logic 1.8 Power Consumption* 1.9 Summary and a Look Ahead Exercises Interview Questions 2 Combinational Logic Design 2.1 Introduction 2.2 Boolean Equations Terminology Sum-of-Products Form Product-of-Sums Form 2.3 Boolean Algebra Axioms Theorems of One Variable Theorems of Several Variables The Truth Behind It All Simplifying Equations 2.4 From Logic to Gates 2.5 Multilevel Combinational Logic Hardware Reduction Bubble Pushing 2.6 X’s and Z’s, Oh My Illegal Value: X Floating Value: Z 2.7 Karnaugh Maps Circular Thinking Logic Minimization with K-Maps Don’t Cares The Big Picture 2.8 Combinational Building Blocks Multiplexers 2:1 Multiplexer Wider Multiplexers Multiplexer Logic Decoders Decoder Logic 2.9 Timing Propagation and Contamination Delay Glitches 2.10 Summary Exercises Interview Questions 2 Combinational Logic Design 2.1 Introduction 2.2 Boolean Equations Terminology Sum-of-Products Form Product-of-Sums Form 2.3 Boolean Algebra Axioms Theorems of One Variable Theorems of Several Variables The Truth Behind It All Simplifying Equations 2.4 From Logic to Gates 2.5 Multilevel Combinational Logic Hardware Reduction Bubble Pushing 2.6 X’s and Z’s, Oh My Illegal Value: X Floating Value: Z 2.7 Karnaugh Maps Circular Thinking Logic Minimization with K-Maps Don’t Cares The Big Picture 2.8 Combinational Building Blocks Multiplexers 2:1 Multiplexer Wider Multiplexers Multiplexer Logic Decoders Decoder Logic 2.9 Timing Propagation and Contamination Delay Glitches 2.10 Summary Exercises Interview Questions 3 Sequential Logic Design 3.1 Introduction 3.2 Latches and Flip-Flops SR Latch D Latch D FIip-Flop Register Enabled Flip-Flop Resettable Flip-Flop Transistor-Level Latch and Flip-Flop Designs* Putting It All Together 3.3 Synchronous Logic Design Some Problematic Circuits Synchronous Sequential Circuits Synchronous and Asynchronous Circuits 3.4 Finite State Machines FSM Design Example State Encodings Moore and Mealy Machines Factoring State Machines Deriving an FSM from a Schematic FSM Review 3.5 Timing of Sequential Logic The Dynamic Discipline System Timing Setup Time Constraint Hold Time Constraint Putting It All Together Clock Skew* Metastability Metastable State Resolution Time Synchronizers Derivation of Resolution Time* 3.6 Parallelism 3.7 Summary Exercises Interview Questions 4 Hardware Description Languages 4.1 Introduction Modules Language Origins Simulation and Synthesis Simulation Synthesis 4.2 Combinational Logic Bitwise Operators Comments and White Space Reduction Operators Conditional Assignment Internal Variables Precedence Numbers Z’s and X’s Bit Swizzling Delays 4.3 Structural Modeling 4.4 Sequential Logic Registers Resettable Registers Enabled Registers Multiple Registers Latches 4.5 More Combinational Logic Case Statements If Statements Truth Tables with Don’t Cares Blocking and Nonblocking Assignments Combinational Logic* Sequential Logic* 4.6 Finite State Machines 4.7 Data Types* SystemVerilog VHDL 4.8 Parameterized Modules* 4.9 Testbenches 4.10 Summary Exercises SystemVerilog Exercises VHDL Exercises Interview Questions 5 Digital Building Blocks 5.1 Introduction 5.2 Arithmetic Circuits Addition Half Adder Full Adder Carry Propagate Adder Ripple-Carry Adder Carry-Lookahead Adder Prefix Adder* Putting It All Together Subtraction Comparators ALU Shifters and Rotators Multiplication* Division* Further Reading 5.3 Number Systems Fixed-Point Number Systems Floating-Point Number Systems* Special Cases: 0, ±∞, and NaN Single-, Double-, and Quad-Precision Formats Rounding Floating-Point Addition 5.4 Sequential Building Blocks Counters Shift Registers Scan Chains* 5.5 Memory Arrays Overview Bit Cells Organization Memory Ports Memory Types Dynamic Random Access Memory (DRAM) Static Random Access Memory (SRAM) Area and Delay Register Files Read Only Memory (ROM) Logic Using Memory Arrays Memory HDL 5.6 Logic Arrays Programmable Logic Array (PLA) Field Programmable Gate Array (FPGA) Array Implementations* 5.7 Summary Exercises Interview Questions 6 Architecture 6.1 Introduction 6.2 Assembly Language Instructions Operands: Registers, Memory, and Constants Registers The Register Set Constants/Immediates Memory 6.3 Programming Program Flow Logical Instructions Shift Instructions Multiply Instructions* Branching Conditional Branches Jumps Conditional Statements If Statements If/else Statements Switch/case Statements* Getting Loopy While Loops For Loops Arrays Bytes and Characters Function Calls Function Calls and Returns Input Arguments and Return Values The Stack Preserved Registers Nonleaf Function Calls Recursive Function Calls Additional Arguments and Local Variables* Pseudoinstructions 6.4 Machine Language R-Type Instructions l-Type Instructions S/B-Type Instructions U/J-Type Instructions Immediate Encodings Addressing Modes Register-Only Addressing Immediate Addressing Base Addressing PC-Relative Addressing Interpreting Machine Language Code The Power of the Stored Program 6.5 Lights, Camera, Action: Compiling, Assembling, and Loading* The Memory Map The Text Segment The Global Data Segment The Dynamic Data Segment The Exception Handler, OS, and I/O Segments Assembler Directives Compiling Assembling Linking Loading 6.6 Odds and Ends* Endianness Exceptions Execution Modes and Privilege Levels Exception Handlers Exception-Related Instructions Exception Handling Summary Signed and Unsigned Instructions Multiplication and Division Set Less Than Branches Loads Floating-Point Instructions Compressed Instructions 6.7 Evolution of the RISC-V Architecture RISC-V Base Instruction Sets and Extensions Comparison of RISC-V and MIPS Architectures Comparison of RISC-V and ARM Architectures 6.8 Another Perspective: x86 Architecture x86 Registers x86 Operands Status Flags x86 Instructions x86 Instruction Encoding Other x86 Peculiarities The Big Picture 6.9 Summary Exercises Interview Questions 7 Microarchitecture 414 7.1 Introduction Architectural State and Instruction Set Design Process Microarchitectures 7.2 Performance Analysis 7.3 Single-Cycle Processor Sample Program Single-Cycle Datapath lw sw R-Type Instructions beq Single-Cycle Control More Instructions Performance Analysis 7.4 Multicycle Processor Multicycle Datapath lw sw R-Type Instructions beq Multicycle Control Fetch Decode MemAdr MemRead MemWB sw R-Type Instructions beq More Instructions Performance Analysis 7.5 Pipelined Processor Pipelined Datapath Pipelined Control Hazards Solving Data Hazards with Forwarding Solving Data Hazards with Stalls Solving Control Hazards Hazard Summary Performance Analysis 7.6 HDL Representation* Single-Cycle Processor Generic Building Blocks Testbench 7.7 Advanced Microarchitecture* Deep Pipelines Micro-Operations Branch Prediction Superscalar Processors Out-of-Order Processor Register Renaming Multithreading Multiprocessors Symmetric Multiprocessors Heterogeneous Multiprocessors Clusters 7.8 Real-World Perspective: Evolution of RISC-V Microarchitecture* 7.9 Summary Exercises Interview Questions 8 Memory Systems 8.1 Introduction 8.2 Memory System Performance Analysis 8.3 Caches What Data is Held in the Cache? How is Data Found? Direct Mapped Cache Multiway Set Associative Cache Fully Associative Cache Block Size Putting it All Together What Data is Replaced? Advanced Cache Design* Multiple-Level Caches Reducing Miss Rate Write Policy 8.4 Virtual Memory Address Translation The Page Table The Translation Lookaside Buffer Memory Protection Replacement Policies* Multilevel Page Tables* 8.5 Summary Epilogue Exercises Interview Questions e9 Embedded I/O Systems 9.1 Introduction 9.2 Memory-Mapped I/O 9.3 Embedded I/O Systems RED-V Board FE310-G002 System-on-Chip General-Purpose Digital I/O GPIO Memory-Mapped I/O Other GPIO Registers Device Drivers Serial I/O Serial Peripheral Interface (SPI) Universal Asynchronous Receiver/Transmitter (UART) Timers Analog I/O D/A Conversion Pulse-Width Modulation A/D Conversion Interrupts 9.4 Other Microcontroller Peripherals Character LCDs VGA Monitor Bluetooth Wireless Communication Motor Control DC Motors Servo Motor Stepper Motor 9.5 Summary eA Digital System Implementation A.1 Introduction A.2 74xx LOGIC Logic Gates Other Functions A.3 Programmable Logic PROMs PLAs FPGAs A.4 Application-Specific Integrated Circuits A.5 Datasheets A.6 Logic Families A.7 Switches and Light-Emitting Diodes Switches LEDs A.8 Packaging and Assembly Packages Breadboards Printed Circuit Boards Putting It All Together A.9 Transmission Lines Matched Termination Open Termination Short Termination Mismatched Termination When to Use Transmission Line Models Proper Transmission Line Terminations Derivation of Z0* Derivation of the Reflection Coefficient* Putting It All Together A.10 Economics B RISC-V Instruction Set Summary eC C Programming C.1 Introduction SUMMARY C.2 Welcome to C C Program Dissection Header: include <stdio.h> Main function: int main(void) Body: printf(“Hello world!\n”) Running a C Program Summary C.3 Compilation Comments C.3.2 define include Summary C.4 Variables Primitive Data Types Global and Local Variables Initializing Variables Summary C.5 Operators C.6 Function Calls C.7 Control-Flow Statements Conditional Statements If Statements If/else Statements Switch/case Statements Loops While Loops Do/while Loops For Loops Summary C.8 More Data Types Pointers Arrays Characters Strings Structures typedef Dynamic Memory Allocation* Linked Lists* Summary C.9 Standard Libraries stdio printf scanf File Manipulation Other Handy stdio Functions stdlib rand and srand exit Format Conversion: atoi, atol, atof math string C.10 Compiler and Command Line Options Compiling Multiple C Source Files Compiler Options Command Line Arguments C.11 Common Mistakes Further Reading Index RISC-V Instruction Set Summary
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