# A Practical Guide to Verilog-A: Mastering the Modeling Language for Analog Devices, Circuits, and Systems

- Length: 353 pages
- Edition: 1
- Language: English
- Publisher: Apress
- Publication Date: 2022-10-07
- ISBN-10: 1484263502
- ISBN-13: 9781484263501
- Sales Rank: #2955420 (See Top 100 Books)

Discover how Verilog-A is particularly designed to describe behavior and connectivity of circuits and system components for analog SPICE-class simulators, or for continuous time (SPICE-based) kernels in Verilog-AMS simulators. With continuous updates since it’s release 30 years ago, this practical guide provides a comprehensive foundation and understanding to the modeling language in its most recent standard formulation.

With the introduction of language extensions to support compact device modeling, the Verilog-A has become today de facto standard language in the electronics industry for coding compact models of active and passive semiconductor devices. You’ll gain an in depth look at how analog circuit simulators work, solving system equations, modeling of components from other physical domains, and modeling the same physical circuits and systems at various levels of detail and at different levels of abstraction.

All industry standard compact models released by Si2 Compact Model Coalition (CMC) as well as compact models of emerging nano-electronics devices released by New Era Electronic Devices and Systems (NEEDS) initiative are coded in Verilog-A. This book prepares you for the current trends in the neuromorphic computing, hardware customization for artificial intelligence applications as well as circuit design for internet of things (IOT) will only increase the need for analog simulation modeling and make Verilog-A even more important as a multi-domain component-oriented modeling language.

Let A Practical Guide to Verilog-A be the initial step in learning the extended mixed-signal Verilog-AMS hardware description language.

What You’ll Learn

- Review the hardware description and modeling language Verilog-A in its most recent standard formulation.
- Code new compact models of active and passive semiconductor devices as well as new models for emerging circuit components from different physical disciplines.
- Extend the application of SPICE-like circuit simulators to non-electronics field (neuromorphic, thermal, mechanical, etc systems).
- Apply the initial steps towards the extended mixed-signal Verilog-AMS hardware description language.

Who This Book Is For

Electronic circuit designers and SPICE simulation model developers in academia and industry. Developers of electronic design automation (EDA) tools. Engineers, scientists and students of various disciplines using SPICE-like simulators for research and development.

Table of Contents About the Author About the Technical Reviewer Acknowledgments Introduction Chapter 1: Lexical Basis Character Set and Tokens Comments Identifiers Simple Identifiers Escaped Identifiers Hierarchical Names Reserved Words System Names Compiler Directives Numerical Literals Integer Literals Real Literals String Literals Operators Punctuators Chapter 2: Basic Types and Expressions Basic Types Integer Types Real Types String Types Expressions Primary Expressions Call Expressions Subscript Expressions Arithmetic Expressions Relational Expressions Logical Expressions Bitwise Expressions Conditional Expressions Concatenated Expressions Expression Evaluation Order Operator Precedence Parenthesized Expressions Short-Circuit Evaluation Expression Containers Assignment Patterns Ranges Chapter 3: Net-Discipline Types Defining Signal Natures Base Natures Derived Natures Predefined Natures Defining Net-Discipline Types Nature Binding Statements Domain Binding Statements Nature Override Statements Deriving Natures from Disciplines Discipline Compatibility Predefined Disciplines Net Declarations Scalar Nets Vector Nets Ground Nets Net Initialization Accessing Net Attributes Chapter 4: Modules and Ports Defining Module Connectivity Declaring Port Directions Declaring Port Types Connecting Modules by Instantiation Explicit Port Mapping Positional Port Mapping Top-Level Instantiation and $root Implicit Nets Instantiation of SPICE Primitives Chapter 5: Parameters Parameter Declarations Simple Parameters Array Parameters Permissible Value Ranges Parameter Aliases Local Parameters Overriding Parameters Instance Parameter Override Parameter Override by Name Parameter Override by Order Hierarchical Parameter Override Hierarchical System Parameters Chapter 6: Paramsets Introducing Paramsets Defining Paramsets Paramset Parameters Parameter Override Statements Other Paramset Statements Paramset Instantiation Chapter 7: Procedural Programming Variables Simple Variables Array Variables Procedural Blocks Analog Blocks Block Procedural Statements Assignment Statements Scalar Assignments Array Assignments Conditional Statements if Statement case Statement Looping Statements while Statement for Statement repeat Statement Chapter 8: Branches Declaring Branches Scalar Branches Vector Branches Port Branches Branch Signals Signal Directions Signal Access Functions Unnamed Branches Contributing Branch Signals Direct Contribution Statements Indirect Contribution Statements Probe Branches Value Retention Switch Branches Chapter 9: Derivative and Integral Operators Time Derivative Operator Case Study: DC Motor Time Integrator Operator Case Study: Chemical Reaction System Circular Integrator Operator Case Study: Voltage-Controlled Oscillator Indirect Contribution Equations Case Study: Accelerometer Probe Derivative Operator Chapter 10: Built-In Math Functions Deterministic Functions Logarithmic and Power Functions Trigonometric Functions Hyperbolic Functions Limiting and Rounding Functions Probabilistic Functions Random Number Generation Function Statistical Distribution Functions Chapter 11: User-Defined Functions Defining Functions Formal Arguments A Return Variable A Procedural Statement Calling Functions Function References Using Functions in Expressions Function Called As Statements Chapter 12: Lookup Tables Table Data Structure Jagged Array Grids Preparing Table Data Lookup Table Function Input Variables and Data Source Control String Chapter 13: Small-Signal Functions AC Analysis AC Stimulus Function Noise Analysis White Noise Function Flicker Noise Function Look-Up Table Noise Functions Correlated Noise Sources Chapter 14: Filters Time-Domain Filters Absolute Delay Filter Transition Filter Slew Filter Frequency-Domain Filters Laplace Transform Filters Zero-Pole Filter Zero-Denominator Filter Numerator-Pole Filter Numerator-Denominator Filter The Z-Transform Filters Zero-Pole Filter Zero-Denominator Filter Numerator-Pole Filter Numerator-Denominator Filter Chapter 15: Events Event Control Statements Global Event Functions Monitored Event Functions Cross Function Last Crossing Function Above Function Timer Function Chapter 16: Runtime Support Elaboration Queries Port Connections Parameter Overrides Simulation Queries Analysis Type Kernel Parameters Dynamic Probing Solver Support Announcing Discontinuity Bounding Time Step Limiting Iteration Steps Simulation Control Announcing Severity Terminating Simulation Chapter 17: Input and Output File Management Opening Files File Positioning Error Status Detecting End-of-File Flushing Output Closing Files Reading Data Reading a Line from a File Reading Formatted Data Displaying and Writing Data Text Output File Output Writing Data to a String Escape Sequences Chapter 18: Generative Programming Generate Blocks Generate Statements Generate Regions Conditional Generation Looping Generation Hierarchy Scope and Names Order of Elaboration Chapter 19: Attributes Introducing Attributes Attribute Assignments Attribute Instances Standard Attributes Simulation Reports Output Variables Port Discipline Override Chapter 20: Compiler Directives File Inclusion Macro Definition Object-like Macros Function-like Macros Undefining Macros Predefined Macros Conditional Compilation Default Transition Directive Appendix Reserved Words in Verilog-A Keywords Other Reserved Words SPICE Compatibility Index

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